1. Field of the Invention
The present invention relates to a duplexer circuit apparatus for selectively connecting either a transmitter or a receiver to one antenna, and in particular, to a duplexer circuit apparatus having an output stage of an integrated cascode amplifier.
2. Description of the Prior Art
Conventionally, GaAs duplexer circuits have been widely used in portable telephones and the like. FIG. 11 shows a circuit diagram of a series and parallel type duplexer circuit of the prior art.
Referring to FIG. 11, the reference numerals F.sub.1 to F.sub.4 denote depletion mode field-effect transistors for duplexer (a field-effect transistor being referred to as an FET hereinafter), while the reference numerals R.sub.d1 to R.sub.d4 denote resistors having a resistance of an order of kilo-ohms for making the drains and sources of the FETs have equivalent electric potentials or voltages. The reference numerals R.sub.g1 to R.sub.g4 denote gate resistors of an order of kilo-ohms of the FETs, while the reference numerals C.sub.1 to C.sub.4 denote capacitors for disconnecting the sources of the FETs F.sub.1 to F.sub.4 from the ground in terms of direct current, the sources being grounded in terms of high frequency.
In the specification, disconnecting a circuit point A from a circuit point B in terms of direct current means that the direct current does not flow between points A and B, and grounding point A in terms of high frequency means that a high frequency signal flows from point A to the ground.
The reference numeral 1 denotes a transmitter connecting terminal, the reference numeral 2 denotes a receiver connecting terminal, and the reference numeral 3 denotes an antenna connecting terminal. The reference numerals 4 and 5 denote terminals, to which control voltages V.sub.TX and V.sub.RX for switching between transmission and reception are applied, respectively. Further, the transmitter connecting terminal 1 is connected to a pull-up voltage V.sub.UP via a pull-up resistor R.sub.UP having a resistance of an order of kilo-ohms for pulling up the electric potential or voltage of a transmission arm circuit located between the terminals 1 and 3 as well as the electric potential or voltage of a reception arm circuit located between the terminals 2 and 3, thereby allowing the duplexer circuit to be controlled by a control voltage having a positive voltage or zero voltage. An operation of the duplexer circuit is shown in Table 1.
TABLE 1 ______________________________________ First Prior Art V.sub.UP V.sub.TX V.sub.RX ______________________________________ Transmission Mode V.sub.dd V.sub.dd 0 V Reception Mode V.sub.dd 0 V V.sub.dd ______________________________________
As is apparent from Table 1, during transmission, the pull-up voltage V.sub.UP and the control voltage V.sub.TX are set to the power source voltage V.sub.dd, while the control voltage V.sub.RX is set to 0 V to turn off the FETs F.sub.1 and F.sub.3 and turn on the FETs F.sub.2 and F.sub.4, so that a high-frequency signal inputted from the transmitter via the terminal 1 is transmitted to the antenna 103 via the FET F.sub.2 and the terminal 3. In this stage, the FET F.sub.3 is in an OFF-state and the FET F.sub.4 is in an ON-state, and therefore, no transmission high-frequency signal is transmitted from the transmitter 101 to the receiver 102. During reception, the pull-up voltage V.sub.UP and the control voltage V.sub.RX are set to the power source voltage V.sub.dd, while the control voltage V.sub.TX is set to 0 V to turn off the FETs F.sub.2 and F.sub.4 and turn on the FETs F.sub.1 and F.sub.3, so that the high-frequency signal that has been received by the antenna 103 and inputted via the terminal 3 is transmitted via the FET F.sub.3 and the terminal 2 to the receiver 102. In this stage, the FET F.sub.2 is in an OFF-state and the FET F.sub.1 is in an ON-state, and therefore, the reception high-frequency signal is not transmitted from the antenna 103 to the transmitter 101. In this case, each of pinch-off voltages V.sub.P of the FETs F.sub.1 to F.sub.4 is set to be lower than the power source voltage V.sub.dd.
FIG. 12 is a circuit diagram showing a constitution of a cascode power amplifier of a second prior art.
Referring to FIG. 12, the reference numerals F.sub.1 and F.sub.2 denote depletion mode FETs for power amplification, the reference numerals R.sub.g1 and R.sub.g2 denote gate resistors for applying a gate voltage to the FETs F.sub.1 and F.sub.2, while the reference numerals C.sub.g1 and C.sub.g2 denote high-frequency bypassing capacitors. The reference symbols L.sub.d and C.sub.d denote an inductance and a capacitor constituting an output impedance matching circuit of the cascode power amplifier, the reference symbols C.sub.t and C.sub.a denote high-frequency coupling capacitors, and the reference numeral L.sub.d2 denotes a high-frequency blocking inductor for supplying a power. The reference numeral 81 denotes an input terminal through which a high-frequency signal to be amplified is inputted, while the reference numeral 82 denotes an output terminal for outputting a high-frequency signal obtained after amplification. Further, the reference numeral V.sub.d2 denotes a power source voltage, the reference numerals V.sub.g1 and V.sub.g2 denote gate voltages to be applied to the FETs F.sub.1 and F.sub.2, respectively.
It is to be noted that the GaAs cascode power amplifier generally has a complicated constitution or circuit and requires a higher voltage to output the required power. Therefore, the GaAs cascode power amplifier is scarcely used in the final stage of a power amplifier, and a source-grounded FET amplifier circuit, which is constituted by only the FET F.sub.1 and obtained by removing the FET F.sub.2 from the circuit shown in FIG. 12, is frequently used.
However, if a case where the power amplifier shown in FIG. 12 and the duplexer circuit shown in FIG. 11 are integrated on an identical chip is put into consideration, then the prior art duplexer circuit, which is constituted by connecting the terminal 1 shown in FIG. 11 to the terminal 82 shown in FIG. 12, has had such a problem that the circuit dimensions become relatively large. In other words, if the power amplifier shown in FIG. 12 and the duplexer circuit shown in FIG. 11 are integrated without modification, the circuit dimensions further increase, meaning that the circuit cannot be compacted.